A new addition to our team! Here is Massimo who works on biosignals, LiDAR, Radar technology, and RISC-V software design with a focus on automotive industry. Welcome to the team, Massimo🤗.
PULP Platform
3,843 posts
PULP Platform
@pulp_platform
A joint effort of @ETH_en, University of Bologna @Unibo + partners for Parallel Ultra-Low Power computing. Boldly designing open hardware since '13.
Joined February 2016
- Live from PULP, you are witnessing the unboxing of Occamy by @LucaBeniniZhFe. Our 432-core Multi-TFLOPs RISC-V-Based 2.5D Chiplet System for Ultra-Efficient (Mini-)Floating-Point Computation came back from assembly at Fraunhofer IZM pulp-platform.org/occamy/! More news coming soon.
- DogeRAM, our chip to test a new Reduced Pin Count (RPC) DRAM interface, is back from packaging. Much DDR, such desin, very chipp, low pin coumt 🤣. WOW. Such a cute chip has to work, right? 😇🐶 Logo by @ZerunJ asic.ethz.ch/2021/Dogeram.h…
- Yun, the first tape-out of Ara, our RISC-V vector extension engine to Ariane is back from manufacturing! We are about to storm the tester room.🤣asic.ethz.ch/2021/Yun.html The Chinese character Yun in this case stands for the Sun 🌞 (not a cloud).
- Live from PULP. We have just started testing Occamy, our 432-core, Multi-TFLOPs RISC-V-Based 2.5D Chiplet System. Keep your fingers crossed🤞😅pulp-platform.org/occamy/
- 2 MOSFETS - N & P CMOS cells with a clean DRC... Here is Matt @matthewvenn rapping at the Tiny Tapeout Workshop at #ETHZurich 😀
00:00 - While we are waiting for the assembly of Occamy pulp-platform.org/occamy/ to finish, we have received samples of the PCB substrate where the interposer will be mounted. Can’t wait to get our hands on the first assembled samples😇.
- Our 64-core RISC-V chip Heartstream just came back from the fab. Thank you @GlobalFoundries UPP for supporting us with this project. Learn more about the chip in our ASIC gallery: asic.ethz.ch/2024/Heartstre…. Time to test🥼🐻!
- And last but not least, Neo in TSMC65 is back from the fab. This is the first design that integrates our Linux-capable Ariane (CVA6) core with an enhanced RPC DRAM memory controller for off-chip communication peripherals: asic.ethz.ch/2022/Neo.html
- Semiengineering recently published an article titled "Minimal RISC-V" in which they discuss the possibility for an even smaller version of a RISC-V processor that could replace 8-bit microcontrollers. PULP got a mention 😀. Check it out: semiengineering.com/a-minimal-risc…
- You can now find "A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR" abstract extension accepted to the VLSISOC24 PhD forum on arXiv: arxiv.org/pdf/2408.08882 @yichao_zh @MarcoBertuletti @saem_r @vanelliale
- Luca has been successfully testing Shaheen (the king of the birds)🦅🙂. Shaheen, a collaboration with Technology Innovation Institute Abu Dhabi, is an IoT processor in GF22 based on CVA6 core with an 8 core PULP cluster. asic.ethz.ch/2022/Shaheen.h…
- Julian's new paper "Ultra-Efficient On-Device Object Detection on AI-Integrated Smart Glasses with TinyissimoYOLO" is now online. GAP9 is used here for enabling computational intensive on-the-edge AI algorithm inference arxiv.org/pdf/2311.01057….
- Another kickoff! We have open-sourced ITA, a hardware accelerator for quantized transformers github.com/pulp-platform/…. ITA exploits parallelism of attention mechanism and 8-bit integer quantization to achieve efficient inference on embedded systems See arxiv.org/pdf/2307.03493
